2025 will be the year of RISC-V desktop!

https://frame.work/si/en/blog/risc-v-mainboard-for-framework-laptop-13-is-now-available

RISC-V Mainboard for Framework Laptop 13 is now available
https://frame.work/si/en/blog/risc-v-mainboard-for-framework-laptop-13-is-now-available
via @frameworkcomputer

"We’re happy to share that DeepComputing’s DC-ROMA RISC-V Mainboard for Framework Laptop 13 is now in stock and shipping in the Framework Marketplace. This is very much a developer-focused board to help accelerate maturing the software ecosystem around RISC-V."

Inside SiFive’s P550 Microarchitecture
https://old.chipsandcheese.com/2025/01/26/inside-sifives-p550-microarchitecture/

"The P550 is a 3-wide out-of-order core with a 13 stage pipeline. Out-of-order execution lets the core move past a stalled instruction to extract instruction level parallelism. It’s critical for achieving high performance because cache and memory latency can be significant limiters for modern CPUs."

RISC-V Made Nice Software Progress In 2024 While Interesting Hardware Still Rare

https://www.phoronix.com/news/RISC-V-2024-Software-Progress

2/n

At last I got that final but important piece for my RISC-V SBC ( @bananapi BPI-F3): the cooler. Now I can finally start compiling some big chunks of code like Qt and KDE software. I do have distributed cross-compiling set up using Icecream, but apparently you can't prevent it scheduling compile jobs locally on SBC and only send them to more powerful computers. Let the fun begin…

1/n

Just got some RISC-V hardware goodies to play with in the following days/months: BPI-F3 SBC by @bananapi with SpacemiT K1 8-core CPU supporting RVV 1.0 vector extensions. Hooked it up to the TV, booted it for the first time from a microSD with the default Bianbu GNU/Linux distro, so far so good. Will try to get Gentoo or openSUSE Tumbleweed with KDE Plasma/software running next.

RISC-V Vector Extension overview
 http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html

"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
[…]
The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."

I had a blast at #RDevDay! I had wonderful pair programming session initiated by Jane He (who is working to get #RStats to compile on #risc_v architecture). We sent a patch to propose a fix of an old bug in `R CMD build`.

Huge thanks to @HeathrTurnr and @R_Contributors for making this happen! It’s great to know that contributing to R core doesn’t have to be scary.

https://bugs.r-project.org/show_bug.cgi?id=18186

Ephraims Wochenrückblick: KW 26, 2024

FOSS News der Woche 24, Krankheitsbedingt in Stichpunkten.

#Wochenrückblick #NVIDIA #RISC_V #Matrix #Framework #Linux

https://gnulinux.ch/ephraims-wochenrückblick-kw-26-2024

Red Hat is hiring a kernel engineer for RISC-V enablement and support. This will be highly Fedora-focused work.

https://redhat.wd5.myworkdayjobs.com/en-US/jobs/job/Software-Engineer---RISC-V-Hardware-Enablement_R-038565

Note that the job is out of the Waterford, Ireland office.

PS: if seriously interested, and if we're at least acquainted, contact me _before_ applying and I'll send you a referral link!