jleightcapnow reading: <i>Retrospective on High-Level Language Computer Architecture</i> [Ditzel and Patterson 1980]: a summary of failed design approaches for<br><br>- reduction of the semantic gap between programming and machine languages<br>- reduction of software development costs<br>- aesthetics ("esoteric")<br><blockquote>[High-level language computers] are aesthetically appealing to those not familiar with modern compiler writing technology. It is acknowledged that code generation may be simpler for a high-level language computer. What needs to be made more fully understood is that a high-level language instruction set does not eliminate the need for compilers, nor does it greatly simplify them. The need and complexity of compilers extends far beyond code generation. The amount of code necessary for preprocessing, lexical analysis, syntax analysis, assembly, optimization, loading, error detection, error recovery and diagnostics often dwarfs the part of the compiler concerned with code generation. The level of the target computer does not seem to have enough of an effect on the size of a compiler to warrant a totally new architecture.<br></blockquote>ref: <a href="https://dl.acm.org/doi/pdf/10.1145/800053.801914" rel="nofollow noopener" target="_blank">https://dl.acm.org/doi/pdf/10.1145/800053.801914</a><br><br>#compilers #computerarchitecture #forth #retrocomputing<br>
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Science News<p>Energy-efficient memory innovation: SOT-MRAM <a href="https://idw-online.social/tags/MemoryTechnology" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>MemoryTechnology</span></a> could replace cache memory in <a href="https://idw-online.social/tags/ComputerArchitecture" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ComputerArchitecture</span></a> in the future // <a href="https://idw-online.social/tags/SustainableComputing" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>SustainableComputing</span></a> <a href="https://idw-online.social/tags/SOTMRAM" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>SOTMRAM</span></a> <a href="https://idw-online.social/tags/SpinOrbitTorque" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>SpinOrbitTorque</span></a> <a href="https://idw-online.social/tags/OrbitalHallEffect" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>OrbitalHallEffect</span></a> @NatureComms @ERC_Research @HorizonEU <a href="https://idw-online.social/tags/MainzUniversity" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>MainzUniversity</span></a> <br><a href="https://nachrichten.idw-online.de/2025/02/06/toward-sustainable-computing-energy-efficient-memory-innovation" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">nachrichten.idw-online.de/2025</span><span class="invisible">/02/06/toward-sustainable-computing-energy-efficient-memory-innovation</span></a></p>
Jure Repinc :linux: :kde:<p>Inside SiFive’s P550 Microarchitecture<br>🔗 <a href="https://old.chipsandcheese.com/2025/01/26/inside-sifives-p550-microarchitecture/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">old.chipsandcheese.com/2025/01</span><span class="invisible">/26/inside-sifives-p550-microarchitecture/</span></a></p><p>"The P550 is a 3-wide out-of-order core with a 13 stage pipeline. Out-of-order execution lets the core move past a stalled instruction to extract instruction level parallelism. It’s critical for achieving high performance because cache and memory latency can be significant limiters for modern CPUs."</p><p><a href="https://mstdn.io/tags/RISCV" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>RISCV</span></a> <a href="https://mstdn.io/tags/RISC_V" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>RISC_V</span></a> <a href="https://mstdn.io/tags/ComputerArchitecture" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ComputerArchitecture</span></a> <a href="https://mstdn.io/tags/CPU" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>CPU</span></a> <a href="https://mstdn.io/tags/CPUs" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>CPUs</span></a> <a href="https://mstdn.io/tags/Processor" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Processor</span></a> <a href="https://mstdn.io/tags/Processors" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Processors</span></a> <a href="https://mstdn.io/tags/Hardware" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Hardware</span></a> <a href="https://mstdn.io/tags/ComputerHardware" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ComputerHardware</span></a> <a href="https://mstdn.io/tags/Eswin" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>Eswin</span></a> <a href="https://mstdn.io/tags/EC7700X" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>EC7700X</span></a> <a href="https://mstdn.io/tags/SiFive" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>SiFive</span></a> <a href="https://mstdn.io/tags/P550" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>P550</span></a></p>
Jure Repinc :linux: :kde:<p>RISC-V Vector Extension overview<br>🔗 <a href="http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">http://</span><span class="ellipsis">0x80.pl/notesen/2024-11-09-ris</span><span class="invisible">cv-vector-extension.html</span></a></p><p>"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.<br>[…]<br>The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."</p><p><a href="https://mstdn.io/tags/RISCV" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>RISCV</span></a> <a href="https://mstdn.io/tags/RISC_V" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>RISC_V</span></a> <a href="https://mstdn.io/tags/RVV" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>RVV</span></a> <a href="https://mstdn.io/tags/ComputerArchitecture" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ComputerArchitecture</span></a> <a href="https://mstdn.io/tags/ISA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ISA</span></a> <a href="https://mstdn.io/tags/InstructionSetArchitecture" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>InstructionSetArchitecture</span></a> <a href="https://mstdn.io/tags/CPU" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>CPU</span></a> <a href="https://mstdn.io/tags/CPUs" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>CPUs</span></a> <a href="https://mstdn.io/tags/processor" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>processor</span></a> <a href="https://mstdn.io/tags/processors" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>processors</span></a></p>
Jure Repinc :linux: :kde:<p>RISC-V State of the Union — current highlights and roadmap of RISC-V by RISC-V's chief architect<br>🎞 <a href="https://yewtu.be/watch?v=_oLVPFQvJbI" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="">yewtu.be/watch?v=_oLVPFQvJbI</span><span class="invisible"></span></a><br>Slides: <a href="https://riscv-europe.org/summit/2024/media/proceedings/plenary/Tue-11-30-Krste-Asanovic.pdf" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">riscv-europe.org/summit/2024/m</span><span class="invisible">edia/proceedings/plenary/Tue-11-30-Krste-Asanovic.pdf</span></a></p><p><a href="https://mstdn.io/tags/RISCV" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>RISCV</span></a> <a href="https://mstdn.io/tags/RISC" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>RISC</span></a> <a href="https://mstdn.io/tags/CPU" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>CPU</span></a> <a href="https://mstdn.io/tags/CPUs" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>CPUs</span></a> <a href="https://mstdn.io/tags/architecture" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>architecture</span></a> <a href="https://mstdn.io/tags/ComputerArchitecture" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ComputerArchitecture</span></a> <a href="https://mstdn.io/tags/processor" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>processor</span></a> <a href="https://mstdn.io/tags/processors" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>processors</span></a> <a href="https://mstdn.io/tags/ISA" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>ISA</span></a> <a href="https://mstdn.io/tags/InstructionSetArchitecture" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>InstructionSetArchitecture</span></a> <a href="https://mstdn.io/tags/hardware" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>hardware</span></a></p>
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