For a school project, I need to choose between 2 Verilog simulator: Verilator or Iverilog.

But I don't know which one to choose.

Any advice ?

#FPGA
#Verilog

#radio #mesh using #reticulum #beechat #kaonic1S #ofdm #FPGA https://youtu.be/OX9hP8WIC0Y

https://beechat.network/product/kaonic-1s/
https://github.com/orgs/BeechatNetworkSystemsLtd/repositories

Me: Mom, I want to watch One Piece on the big screen!
Mom, who is an FPGA development board: We have One Piece on the big screen at home.

Verilog-based image stream decoder. A Ruby script sends 96x64 256 color images, each with a unique palette, over UART at 921600 baud at around 13 FPS, and the ULX3S renders them on the OLED screen with double-buffered palettes and image data. Definitely the most complex serial protocol-driven stuff I've written so far. I may try moving the image data storage over to SDRAM, just because. #fpga

There are few more horrid things in my job than flashing Firmware on QSPI memory with #Vivado. #fpga

Just released version 0.1 of TinyGo-TKey to develop apps for the Tillitis TKey-1 using TinyGo!

https://github.com/hybridgroup/tinygo-tkey

TKey-1 is an open source, open hardware FPGA-based USB security token from the awesome team at Tillitis:
https://tillitis.se/

No i po piwie. Znaczy po @piwo -ie.

Najciekawsze rozmowy i projekty:
- Otwarte rdzenie RISC-V na #FPGA na których działa #Linux https://kuznia-rdzeni.org/ @coreforge
- smak wafli krzemowych
- Demo #Bevy w terminalu przez #ratatui (JAK???) @j_g00da
- rozmowa o połączeniu wyrzucania działającego sprzętu z rozwojem dzisiejszej ekonomii
- "sprzedam #mikroskop elektronowy w okazyjnej cenie" @q3k

#piwo2025 #riscv @dos

And suddenly there it was, an accurate #FPGA implementation of the #SNES on the #MiSTer. That was an awesome moment for #retrogaming.

So, I’m not a programmer, I can usually hack things to make them work.
But, I’m stuck so I’m asking for advise please.
I’m using windows (not for much longer) and I’ve got a neorisc-v onto my Alchitry au board (it gets to the bootloader) but I can’t seem to compile any of the examples. I found a prebuilt windows compiler (.zip) but I’m lost what to do next. Can anyone help?
#riscv #fpga

turbo

Show HN: Icepi Zero – The FPGA Raspberry Pi Zero Equivalent

Link: https://github.com/cheyao/icepi-zero
Discussion: https://news.ycombinator.com/item?id=44115853

Siped Tang Console is an FPGA dev board that can also be used as a retro console with downloadable NES, SNES, Game Boy, and Amiga cores, among others. It sells for $69 and up ($99 and up for a higher-performance version). #Sipeed #FPGA #RetroGaming #SipeedTangConsole https://www.cnx-software.com/2025/05/27/sipeed-tang-console-a-gowin-gw5ast-gw5at-board-with-60k-or-138k-lut-for-fpga-development-and-retro-gaming/

OK this is pretty cool. A project called DigitalJS can give you a visual layout of all of the logic that'll go into a Verilog design, using Yosys to do the generation. Being able to see what's being ultimately produced helps me, a much more visual person, understand when I've flubbed something that generates too much logic. I already optimized one piece of the display RAM using it. It's at https://digitaljs.tilk.eu/ but you can also run it locally. #fpga #verilog #ulx3s

I managed to get a 6502 CPU running on the ULX3S and wrote a 16 color indexed display RAM module for it. The CPU also has access to all the buttons and the LEDs, which are counting up the current low byte of display RAM. Its the most complex bit of Verilog I've written so far. I hope to add basic sound support next, and then I'll have made my own little toy console to mess with. #ulx3s #fpga #6502CPU

#dearmastodon #lazyweb

Is there a tool besides the pop-up on the default browser that can let me explore relevant hashtags for #mastodon?

I did a web-search and it shows #hashtags for other platforms with things like #love, #fashion, etc. but obviously I don't want to use a generic list like that.

But it would be nice to know what people are following and/or posting to so I can match their interests. Mostly for #electronics, #fpga, etc.

Exploring the Future of FPGA Innovations: Insights from FCCM 2025

The IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2025 showcased groundbreaking advancements in FPGA technology, focusing on the future beyond Moore's Law. With a...

https://news.lavx.hu/article/exploring-the-future-of-fpga-innovations-insights-from-fccm-2025

I've finally set up my Matrix account!

I couldn't find any public #retrocomputing, #AtariST, #FPGA or #demoscene chat rooms though.

I can just wait and count on the Discord enshittification process to see the different communities switch to Matrix. Not sure how long it will take though.

RT: @eli.lipsitz.net‬ (bluesky) There’s been a lot of interest in Game Bub, so I’m going to be launching a crowdfunding campaign through
@crowdsupply!

Sign up for updates and to hear when the campaign goes live:
https://www.crowdsupply.com/second-bedroom/game-bub

This will be an assembled product, not just a kit!

src:https://bsky.app/profile/eli.lipsitz.net/post/3loh6epj7m22w
---

This is #opensource #FPGA #GameBoy and #GameBoyAdvance / #gba clone

#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?

I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.