@loke Quoting simh:

The VAX has a variable length instruction format with up to six operands:

opcode byte
operand 1 specifier
:
operand n specifier

Each operand specifier is a byte consisting of an addressing mode, a
register, and possibly 1-8 bytes of extension:

number name extension mnemonic operation

0-3 short literal - #n op <- specifier
4 index - [Rn] index by Rn
5 register - Rn op <- Rn
6 register def - (Rn) op <- M[Rn]
7 autodecrement - -(Rn) Rn <- Rn - length
op <- M[Rn]
8 autoincrement - (Rn)+ op <- M[Rn]
Rn <- Rn + length
9 auto deferred - @(Rn)+ op <- M[M[Rn]]
Rn <- Rn + 4
A byte displ byte d d(Rn) op <- M[Rn + sxt.d]
B byte displ def byte d @d(Rn) op <- M[M[Rn + sxt.d]]
C word displ word d d(Rn) op <- M[Rn + sxt.d]
D word displ def word d @d(Rn) op <- M[M[Rn + sxt.d]]
E long displ long d d(Rn) op <- M[Rn + d]
F long displ def long d @d(Rn) op <- M[M[Rn + d]]

When the general register is the PC, certain modes are forbidden, and
others have special interpretations:

4F index fault
5F register fault
6F register def fault
7F autodecrement fault
8F immediate 1-8B #imm op <- imm
9 absolute 4B @#imm op <- M[imm]
A byte relative byte d d(Rn) op <- M[PC + sxt.d]
B byte rel def byte d @d(Rn) op <- M[M[PC + sxt.d]]
C word relative word d d(Rn) op <- M[PC + sxt.d]
D word rel def word d @d(Rn) op <- M[M[PC + sxt.d]]
E long relative long d d(Rn) op <- M[PC + d]
F long rel def long d @d(Rn) op <- M[M[PC + d]]

This routine is the instruction decode routine for the VAX. It
is called from the simulator control program to execute instructions
in simulated memory, starting at the simulated PC. It runs until an
enabled exception is encountered.