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#CPUs

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Radargit

Core Ultra 9 285: Performance Tests in Benchmarks and Full Specs

Intel's latest Core Ultra 9 285 is here — and we've put it through the gauntlet. From raw benchmark scores to full hardware specs, find out how it stacks up against the competition.

Read the full breakdown:
radargit.com/2025/04/11/core-u

Is this the new king of high-performance CPUs? Let’s talk.

Radargit · Core Ultra 9 285: performance tests in benchmarks and full specsIntel® Core™ Ultra 9 Processor 285 , We tested this 24-core powerhouse in games, AI tasks, and 4K rendering. Full specs, benchmarks,
#Intel#CoreUltra9#Benchmarks
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Jure Repinc :linux: :kde:

RISC-V Mainboard for Framework Laptop 13 is now available
🔗 frame.work/si/en/blog/risc-v-m
via @frameworkcomputer

"We’re happy to share that DeepComputing’s DC-ROMA RISC-V Mainboard for Framework Laptop 13 is now in stock and shipping in the Framework Marketplace. This is very much a developer-focused board to help accelerate maturing the software ecosystem around RISC-V."

FrameworkRISC-V Mainboard for Framework Laptop 13 is now available
#RISCV#RISC_V#laptop
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Jure Repinc :linux: :kde:

Inside SiFive’s P550 Microarchitecture
🔗 old.chipsandcheese.com/2025/01

"The P550 is a 3-wide out-of-order core with a 13 stage pipeline. Out-of-order execution lets the core move past a stalled instruction to extract instruction level parallelism. It’s critical for achieving high performance because cache and memory latency can be significant limiters for modern CPUs."

Chips and Cheese · Inside SiFive’s P550 Microarchitecture
More from clamchowder
#RISCV#RISC_V#ComputerArchitecture
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W3C Developers

The @w3c #WebAssembly Core Specification is now a #CandidateRecommendation
▶️ w3.org/TR/wasm-core-2/
#timetoimplement

This doc. outlines release 2.0 of the core WebAssembly standard, a secure, portable, low-level code format. The update improves #performance, including support for SIMD (Single Instruction Multiple Data) to enhance #parallel processing on compatible #CPUs.

Check which #WASM features are supported across #browsers in
webassembly.org/features/

Feedback: github.com/WebAssembly/spec/is

WebAssembly
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Jure Repinc :linux: :kde:

RISC-V Vector Extension overview
🔗 0x80.pl/notesen/2024-11-09-ris

"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
[…]
The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."

0x80.plRISC-V Vector Extension overview
#RISCV#RISC_V#RVV
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